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Dankook Univ. Power Electronics Lab.

prof. : June-Seok Lee (이준석)

ADR : Rm #407, 2nd Eng. Building, Dankook University 152, Jukjeon-ro, Suji-gu, Yongin-si, Gyeonggi-do, 16890, Korea

TEL : +82-31-8005-3826 | E-mail : ljs@dankook.ac.kr

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Publication

Paper Book Patents Articles

Dongho Choi, Jiho Ju, Jin-Hyuk Park, and June-Seok Lee, "Dead-Time Compensation Technique Reflecting the Ratio of the Polarity Based on the Current Prediction in Cascaded H-bridge Multilevel Inverter," in Proc. 2023 IECON

In Proc 2023
PEEMS

  • Dec. 1, 2023

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1. Authors: Dongho Choi, Jiho Ju, Jin-Hyuk Park, and June-Seok Lee
2. Title: Dead-Time Compensation Technique Reflecting the Ratio of the Polarity Based on the Current Prediction in Cascaded H-bridge Multilevel Inverter
3. Published in: IECON 2023- 49th Annual Conference of the IEEE Industrial Electronics Society
4. Date of Conference: 16-19 October 2023
5. Conference Location: Singapore
6. Abstract
: This article proposes a current-prediction-based dead-time compensation technique designed to reduce zero-current-clamping in grid-connected cascaded H-bridge multilevel inverters (CHMI) using phase-shifted PWM (PS-PWM). In general, dead-time compensation is achieved by adding an offset voltage, derived from the voltage drop during dead-time. This offset voltage formula incorporates a polarity of grid current. However, when this polarity undergoes a transition within the control period, effective compensation is hindered, leading to the zero-current-clamping phenomenon. This effect is more pronounced in practical systems that utilize the shadow register function of a digital signal processor (DSP). In CHMI systems, particularly those with a lower switching frequency, current distortion becomes more prominent. In the proposed technique, the polarity ratio of the grid current reference during a control period is determined using current reference predictions, facilitating the generation of a precise offset voltage. Consequently, there is a notable attenuation of the odd-harmonic components intrinsic to the grid current, leading to a reduction of the zero-current-clamping phenomenon. The validity of this technique is demonstrated through simulation results based on a 7-level CHMI configuration.
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